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The program marks the first joint semiconductor competition developed by Brazil and Malaysia, created to strengthen international collaboration and develop the next generation of chip design talent.

Registration Opens: 7 May 2026

300

Spots

ChipInventor

EDA Platform

100%

Free

About the eXperience

Executed by Von Braun Labs and inspired by the ChampionCHIP program conducted in Brazil, this edition is developed in partnership with the Advanced Semiconductor Academy of Malaysia (ASEM) and with the support of the Embassy of Brazil in Malaysia, through the Innovation Diplomacy Program of the Brazilian Ministry of Foreign Affairs. The program aims to train university students in microelectronics, a strategic field for AI, telecommunications, and automation facing a global shortage of specialists—over 1 million professionals will be needed by 2030.

Micro electronics

A fast-growing and hard-to-access field with subfields requiring highly trained professionals.
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Complete Training

Not just a competition — it is a complete training journey that takes students to the next level.
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International Partnership

Developed in partnership with Von Braun Labs, ASEM, and the Embassy of Brazil in Malaysia.
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ChipInventor Access

Cloud-based chip design tool made available to participants.
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ChampionChip Stages

The competition happens across multiple stages, allowing participants to design their own digital or analog projects using ChipInventor.

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Sign up for the program

Current Stage

Training

Online and hands-on modules

Design Challenge

Development with ChipInventor

AWS Cloud FPGA Prototype

FPGA Prototyping on AWS Cloud

Experience the Technology Behind Modern Systems

Join the ChampionChip Experience and explore how everything works — from chip to system.

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Learning Track - 85H

Modules & Syllabus

Explorer - Digital Fundamentals

Introductory module focused on core digital design concepts.

  • Introduction to Semiconductors
  • Boolean Logic and Logic Gates
  • Combinational Logic
  • Arithmetic Logic Unit (ALU)
  • Flip-Flop
  • Register
  • Counter
  • Building a Finite State Machine (FSM)
  • Validation a Finite State Machine (FSM)
  • Final Project

Designer – Digital Projects, Integration & Simulation

Hands-on module focused on building and simulating digital systems.

  • Introduction to Simulation
  • Priority Arbiter
  • PWM Generator
  • Synchronous FIFO
  • FIR Filter
  • Cache System
  • UART (Transmitter, Receiver, Integraion & Testing)
  • Dynamic PWM System Implementation

Innovator – Digital Backend

Focus on backend design flow and chip implementation.

  • Introduction to Backend Processes
  • RTL Validation
  • Synthesis and Netlist Analysis
  • Layout and Timing Analysis
  • Post-Synthesis Validation
  • Final Analysis and GDSII File

Pioneer – RISC-V Core Design

Advanced module focused on designing a full processor core.

  • Introduction to RISC-V Architecture
  • Arithmetic Logic Unit (RISC-V)
  • Register File
  • Immediate Generator
  • Control Unit
  • Datapath Integration
  • Core Testbench Creation
  • Validation of Arithmetic Instructions
  • Validation of Memory and Branch Instructions
  • Final Project

Cloud FPGA – AWS-Based Prototyping

Introduction to cloud-based hardware prototyping.

  • What is an FPGA
  • AWS F2 FPGA
  • AXI4-Lite Protocol
  • OCL 32-bit
  • Setup on ChipInventor
Capstone

Challenge Stages

STAGE 03

Real Slicon Constraints

Design Challenge

SkyWater 130nm PDK

In this stage, participants bring their designs closer to real silicon by working with the SkyWater 130nm PDK, applying industry-relevant constraints and optimization strategies.

STAGE 04

Real Hardware Execution

AWS FPGA Prototype

AWS FPGA F2

In the final stage, participants deploy their optimized system into a real hardware environment using AWS FPGA F2, enabling full system validation beyond simulation.

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Section A: Personal Information

Section B: Academic Information

The Academic Transcript and Letter of Completion are both required documents which will still be requested upon confirmation.

Section C: General Information

Shortlisted applicants will receive further details on the next stages.